Signal switching apparatus and program

ABSTRACT

A signal switching apparatus is provided which is capable of performing checking in a manner that a plurality of output channels can be discriminated in checking the assignment of the plurality of output channels to buses to which signals are input. A plurality of signals input to a mix bus comprised of six buses are selectively output to two analog outputs in accordance with assignment performed by an output assigning device. First checking signals for three channels among six channels from a first oscillator are directly input to an adjuster, and first checking signals for the rest of the six channels from the first oscillator are input to a signal switching device. Second checking signals for all of three channels from a second oscillator are input to the checking signal switching device. The checking signal switching device selectively outputs the input first or second checking signals to the adjuster. The adjuster selectively outputs the input first and second checking signals to desired buses and at desired volumes in accordance with settings of the adjuster, and the first and second checking signals are output via respective analog outputs in accordance with settings of the output assigning device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a signal switching apparatus such as amixer, which inputs a plurality of signals to a mix bus, assigns theinput signals to respective desired output channels assigned torespective buses of the mix bus, and outputs the signals via the outputchannels, as well as a program for controlling the signal switchingapparatus.

2. Description of the Related Art

Conventionally, as described e.g. in “Instruction Manual for YamahaDigital Production Console DM2000”, a signal switching apparatus such asa mixer for use at a broadcast station or the like has been known. Thissignal switching apparatus is capable of inputting a plurality of inputsignals to a mix bus comprised of a large number of buses, mixing them,subjecting them to predetermined processing, and outputting them viaoutput channels assigned to buses of the mix bus. In general, thissignal switching apparatus is provided with an oscillator, whichgenerates a predetermined checking signal for ascertaining/checking inadvance whether or not the actual assignment of buses to which signalsare to be input and output channels via which the signals from therespective buses are to be output coincides with the user's intention.The user causes the checking signal generated from the oscillator to beinput to the mix bus, and listens to sounds output via the outputchannels, thus checking settings as to output channels for therespective buses.

In the above described conventional signal switching apparatus, however,when checking is performed by inputting one signal from the oscillatorto a plurality of (e.g. two) buses to which a plurality of (e.g. L/R)output channels are assigned, the same signal is outputted from theplurality of buses, and hence it is necessary to check outputs via therespective output channels while consciously trying to discriminatebetween the output channels. Therefore, it is not easy to performchecking.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a signalswitching apparatus which is capable of easily performing checking in amanner that a plurality of output channels can be discriminated inchecking the assignment of the plurality of output channels to buses towhich signals are input, as well as a program for controlling the signalswitching apparatus.

To attain the above object, in a first aspect of the present invention,there is provided a signal switching apparatus that assigns a pluralityof signals input to a mix bus comprising a plurality of buses, torespective desired output channels assigned to respective ones of thebuses, and outputs the plurality of signals via the output channels,comprising a plurality of checking signal generating devices thatgenerate checking signals different from each other, and a checkingsignal input device that causes the checking signals generated by theplurality of checking signal generating devices to be selectively inputto respective desired buses of the mix bus.

Preferably, the plurality of buses are grouped into a plurality ofgroups.

More preferably, the checking signal input device comprises a selectingdevice that selects desired checking signals to be input to part of theplurality of groups from among the plurality of checking signals, andthe checking signals selected by the selecting device are input to allof the buses belonging to the part of the plurality of groups.

More preferably, the checking signal input device causes part of theplurality of checking signals to be always input to all of busesbelonging to a predetermined part of the plurality of groups.

According to the first aspect of the present invention, a plurality ofdifferent checking signals generated are selectively input to desiredbuses of the mix bus, and are output via the output channels assigned tothe respective buses. As a result, it is possible to discriminatebetween the plurality of output channels and hence easily perform thechecking.

To attain the above object, in a second aspect of the present invention,there is provided a program executed by a computer, for assigning aplurality of signals input to a mix bus comprising a plurality of buses,to desired output channels assigned to respective ones of the buses andoutputting the plurality of signals via the output channels, comprisinga checking signal generating module for generating a plurality ofchecking signals different from each other, and a checking signal inputmodule for causing the plurality of checking signals generated by thechecking signal generating module to be selectively input to respectivedesired buses of the mix bus.

A computer-readable storage medium storing the above program constitutesthe present invention.

The above and other objects, features, and advantages of the inventionwill become more apparent from the following detailed description takenin conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the entire construction of a signalswitching apparatus according to an embodiment of the present invention;

FIG. 2 is a diagram showing in detail the configurations of a signalprocessing circuit and an input/output interface;

FIG. 3 is a diagram showing the internal configuration of one inputcomputing device; and

FIG. 4 is a diagram showing an example of an operator setting screenview.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will now be described in detail with reference tothe drawings showing a preferred embodiment thereof.

FIG. 1 is a block diagram showing the entire construction of a signalswitching apparatus according to an embodiment of the present invention.This signal switching apparatus is implemented by a mixer, for example.

The signal switching apparatus according to the present embodiment iscomprised of a RAM 11, a ROM 12, a signal processing circuit 14, adetecting circuit 15, a display circuit 16, and a storage device 20, aCPU 10, and a communication bus 13 via which the above components areconnected to each other. Further, an operating section 18 is connectedto the detecting circuit 15, and a display section 19 comprised of anLCD (Liquid Crystal Display), for example, is connected to the displaycircuit 16. An input/output interface (I/F) 17, which provides interfacefor inputting and outputting various kinds of signals, is connected tothe signal processing circuit 14.

The operating section 18 has a plurality of switches, not shown, forinputting various kinds of information. The detecting circuit 15 detectsthe depression of each of the switches provided in the operating section18. The display circuit 16 provides control to display various kinds ofinformation such as a setting screen view on the display 19. The CPU 10controls the overall operation of the signal switching apparatus. TheROM 12 stores control programs to be executed by the CPU 10, variouskinds of tables, and a variety of data. The RAM 11 temporarily storesvarious kinds of input information, various kinds of flags, buffer data,calculation results, and so forth. The storage device 20 drives astorage medium, not shown, such as a floppy (registered trademark) disk,in which a variety of application programs such as the above mentionedcontrol programs and a variety of data can be stored.

FIG. 2 is a diagram showing in detail the configurations of the signalprocessing circuit 14 and the input/output interface 17. The signalprocessing circuit 14 includes a group of buses consisting of buses 1 to4 and stereo buses L and R, and the group of buses (six buses in thepresent embodiment) constitutes a mix bus MB for mixing input signals.An analog input 21, a digital input 22, an input assigning device 23,and input computing devices 24(1) to 24(10) are provided as componentparts for inputting signals to the mix bus MB; an output computingdevice 25, an output assigning device 26, and analog outputs 27 and 28are provided as component parts for outputting signals input to the mixbus MB. In FIG. 2, the analog input 21, digital input 22, and analogoutputs 27 and 28 correspond to the input/output interface appearing 17in FIG. 1, and the other component parts correspond to the signalprocessing circuit 14.

Signals for five channels are input to the input assigning device 23 viaeach of the analog input 21 and the digital input 22. The inputcomputing devices 24 are identical in construction with each other andcorresponds in number to the maximum number of (ten in the presentembodiment) input signals. The signals input to the input assigningdevice 23 are input to the corresponding ones of the input computingdevices 24 for respective input channels. Namely, one input signal isinput to one input computing device 24.

FIG. 3 is a diagram showing the internal configuration of one of theinput computing devices 24. Each of the input computing devices 24 iscomprised of an equalizer (EQ) 31, a delay device (DL) 32, a send-leveladjuster 33, and switches 34. The equalizer 13 adjusts frequencycharacteristics of an input signal. The delay device 32 delays the inputsignal by a predetermined period of time to cause a delay in output ofthe input signal to the mix bus MB. The send-level adjuster 33 adjuststhe volume (the amount of attenuation from a predetermined volume) ofthe input signal, which is sent to the mix bus MB. The switches 34correspond in number to the number of buses (six in the presentembodiment) constituting the mix bus MB, and are used for turning on/offoutput to the respective buses of the mix bus MB.

Referring again to FIG. 2, the signals input to the respective inputcomputing devices 24 are subjected to processing by the respectiveequalizers 31, delay devices 32, and send-level adjusters 33, and areinput to the buses of the mix bus MB, which correspond to switches 34which are in an ON state.

The signals input to the mix bus MB are input to the output computingdevice 25 in six channels corresponding in number to the number of busesconstituting the mix bus MB. Although not illustrated, the outputcomputing device 25 is comprised of component parts for six channels,which are identical in function with the above described equalizer 31,delay device 32, and send-level adjuster 33, and correspond to therespective channels (or correspond to the respective buses), and signalsin the respective channels are subjected to processing by the componentparts and are separately output to the output assigning device 26.

The output assigning device 26 assigns the signals input from the outputcomputing devices 25 to output channels, and selectively outputs thesignals to the analog output 27 or to the analog output 28. It isassumed in the present embodiment that the analog output 27 is for an L(left) channel, and the analog output 28 is for an R (right) channel.

The statuses of the component parts in the input computing devices 24and the assignment of the output channels in the output assigning device26 are set through the operation of the operating section 18 (refer toFIG. 1).

As shown in FIG. 2, the signal processing circuit 14 is further providedwith a checking signal switching device 29 and an adjusting device(adjuster) 30 in addition to two oscillators OSC1 and OSC2. Theoscillators OSC1 and OSC2 are checking signal generators that generatedifferent checking signals. The oscillator OSC1 outputs first checkingsignals for six channels, and the oscillator OSC2 outputs secondchecking signals for three channels. The first checking signals forthree of the six channels from the oscillator OS1 are directly input tothe adjuster 30, and the first checking signals for the rest of the sixchannels from the oscillator OS1 are input to the checking signalswitching device 29. The second checking signals for all of the threechannels are input to the checking signal switching device 29. Thechecking signal switching device 29 and the adjuster 30 constitute achecking signal input device.

The checking signal switching device 29 is comprised of a change-overswitch, which selectively outputs the first checking signals for threechannels from the oscillator OSC1 or the second checking signals forthree channels from the oscillator OSC2 to the adjuster 30.

The adjuster 30 causes the first checking signals input form theoscillator OSC1 and the first or second checking signals input via thechecking signal switching device 29 to be input to the mix bus MB. Inthe present embodiment, the first checking signals for three channelsdirectly input from the oscillator OS1 to the adjuster 30 are input tothe buses 1 and 3 and the stereo bus L (first bus group) so that theycan be used for checking paths via which signals for the L (left)channel are output. On the other hand, the checking signals for threechannels input via the checking signal switching device 29 are input tothe buses 2 and 4 and the stereo bus R (second bus group) so that theycan be used for checking paths via which signals for the R (left)channel are output. It should be noted that to which buses the first andsecond checking signals are to be input is not limited to the above.

The adjuster 30 is comprised of component parts, not shown, which areidentical in construction with the send-level adjuster 33 and theswitches 34 provided in the input computing device 24, and it isconfigured such that checking signals are input only to desired busesand at desired volumes in accordance with settings of these componentparts. A description will be given later of settings of the adjuster 30and settings of the checking signal switching device 29 with referenceto FIG. 4.

Similarly to the input signals via the analog input 21 and the digitalinput 22, the checking signals input to the mix bus MB are selectivelyoutput via the analog outputs 27, 28 according to settings of the outputcomputing device 25 and the output assigning device 26.

FIG. 4 is a diagram showing an example of an oscillator setting screenview, which is displayed on the display section 19 (refer to FIG. 1) inan oscillator setting mode. In FIG. 4, an oscillator on/off field 41specifies whether to activate or deactivate the oscillators OSC1 andOSC2. For example, if the oscillator on/off field 41 is set to “ON”,both the oscillators OSC1 and OSC2 are activated to generate therespective first and second checking signals, and on the other hand, ifthe oscillator on/off field 41 is set to “OFF”, both the oscillatorsOSC1 and OSC2 are deactivated.

A waveform selection field 43 specifies settings of the checking signalswitching device 29 by selection of “oscillator OSC1” or “oscillatorOSC1/2”. That is, if “oscillator OSC1” is selected, the checking signalswitching device 29 outputs the first checking signals for threechannels input from the oscillator OSC1 to the adjuster 30, and if“oscillator OSC1/2” is selected, the checking signal switching device 29outputs the second checking signals for three channels input from theoscillator OSC2 to the adjuster 30.

The types e.g. waveform and frequency of the checking signals to begenerated by the oscillators OSC1 and OSC2 can be selected arbitrarilyor from among a plurality of options; for example, “sine curve 1 kHz”can be selected. The selected types of checking signals for therespective oscillators OSC1 and OSC2 are set on a setting screen view,not shown.

An oscillator send-level field 42 specifies settings of theabove-mentioned send-level adjuster, not shown, provided in the adjuster30. That is, the oscillator send-level field 42 is used for adjustingthe volumes (amounts of attenuation) of the first and second checkingsignals, which are to be input to the adjuster 30 and output to the mixbus MB. The volumes of the first and second checking signals can beadjusted for the respective corresponding buses of the mix bus MB. Thesend-level may be adjusted collectively for signals which are to beinput to the adjuster 30. Alternatively, a send-level adjuster may bedisposed immediately after each of the oscillators OSC1 and OSC2 so thatthe send-level can be adjusted for each of the oscillators OSC1 andOSC2.

A bus output setting field 44 specifies settings of the above-mentionedswitches, not shown, provided in the adjuster 30. That is, by selectinga bus as a destination, it is possible to make a setting as to whetheror not each of the first and second checking signals input to theadjuster 30 is to be output to the corresponding bus of the mix bus MB.For example, when only the buses 3 and 4 are selected, the firstchecking signal is input from the adjuster 30 to the bus 3 and the firstor second checking signal is input from the adjuster 30 to the bus 4.

With the above arrangement, a checking process for ascertaining inadvance whether or not the actual assignment of output channels torespective buses coincides with the user's intention is carried out in amanner described below. A description will be given of how the checkingprocess is carried out to check outputs from the two buses 3 and 4 usingthe two oscillators OSC1 and OSC2, for example.

After setting the component parts in the input computing devices 24 andcarrying out assignment of the output channels in the output assigningdevice 26, the user causes the oscillator setting screen appearing inFIG. 4 to be displayed, sets the oscillator on/off field 41 to “ON”,sets the waveform selection field 43 to “oscillator OSC1/2”, sets thebus output setting field 44 such that the buses 3 and 4 are selected,and adjusts the volume as appropriate in the oscillator send-level field42. It is assumed here that in the output assigning device 26, therespective output channels of the buses 3 and 4 of the mix bus MB areassigned to the analog outputs 27 and 28, respectively.

According to the above described settings, among the first checkingsignals for three channels directly input from the oscillator OSC1 tothe adjuster 30, only one corresponding to the bus 3 is input to the bus3. The first checking signals for the other three channels input fromthe oscillator OSC1 to the checking signal switching device 29 areblocked by the checking signal switching device 29, so that they are notinput to the adjuster 30 and the mix bus MB. On the other hand, thesecond checking signals for three channels input from the oscillatorOSC2 to the checking signal switching device 28 are input to theadjuster 30, and only one of them corresponding to bus 4 is input to thebus 4.

Then, the first checking signal is output from the bus 3 to the analogoutput 27 via the output computing device 25 and the output assigningdevice 26, and the second checking signal is output from the bus 4 tothe analog output 28 via the output computing device 25 and the outputassigning device 26. By listening to sounds output via the analogoutputs 27 and 28, the user can ascertain whether tones are sounded ornot via his/her desired output channels. In particular, since the firstand second checking signals are different from each other and outputsounds are different from each other, outputs via the L/R channels canbe correctly checked at a time.

According to the present embodiment, the two oscillators OSC1 and OSC2generate the respective first and second checking signals different fromeach other, so that the first and second checking signals areselectively input to the respective desired buses of the mix bus MB, andare output as sounds according to the assignment of the output channelsin the output assigning device 26. As a result, checking can be easilyperformed with very few errors, making it unnecessary to check outputsvia the respective L/R channels while consciously trying to discriminatebetween them. Thus, checking can be easily performed in a manner thatthe plurality of output channels can be discriminated.

Incidentally, it is possible to perform checking using a single checkingsignal as in the prior art by setting the waveform selection field 43 to“oscillator OSC1”.

The number of buses constituting the mix bus MB is not limited to six asabove.

Although in the present embodiment, checking is performed in a mannerdiscriminating between the L/R channels, the present invention is notlimited to this, but the number of channels subjected to checking may beset to three or more by increasing the number of oscillators. Forexample, it is assumed that a center channel is provided in addition tothe L channel and the R channel, and a setting is made such that signalsfrom the buses 1 and 4 are output via the L channel, signals from thebus 2 and the stereo bus L are output via the center channel, signalsfrom the bus 3 and the stereo bus R are output via the R channel. Inthis case, from oscillators OSC1, OSC2, and OSC3 provided for generatingrespective first, second, and third checking signals different from eachother, the first checking signals are input to the buses 1 and 4, thesecond checking signal are input to the bus 2 and the stereo bus L, andthe third checking signals are input to the bus 3 and the stereo bus R.In this way, the three channels, i.e. the L channel, center channel, andR channel can be checked at a time.

It is to be understood that the object of the present invention may alsobe accomplished by supplying a system or an apparatus with a storagemedium in which a program code of software which realizes the functionsof the above described embodiment is stored, and causing a computer (orCPU or MPU) of the system or apparatus to read out and execute theprogram code stored in the storage medium.

In this case, the program code itself read from the storage mediumrealizes the functions of the above described embodiment, and hence theprogram code and a storage medium on which the program code is storedconstitute the present invention. The storage medium for supplying theprogram code is not limited to a ROM, and a floppy (registeredtrademark) disk, a hard disk, an optical disk, a magnetic-optical disk,a CD-ROM, a CD-R, a CD-RW, a DVD-ROM, a DVD-RAM, a DVD−RW, a DVD+RW, anNV-RAM, a magnetic tape, a nonvolatile memory card, and a downloadcarried out via a network may be used.

Further, it is to be understood that the functions of the abovedescribed embodiment may be accomplished not only by executing theprogram code read out by a computer, but also by causing an OS(operating system) or the like which operates on the computer to performa part or all of the actual operations based on instructions of theprogram code.

Further, it is to be understood that the functions of the abovedescribed embodiment thereof may be accomplished by writing the programcode read out from the storage medium into a memory provided in anexpansion board inserted into a computer or a memory provided in anexpansion unit connected to-the computer and then causing a CPU or thelike provided in the expansion board or the expansion unit to perform apart or all of the actual operations based on instructions of theprogram code.

1. A signal switching apparatus comprising: a plurality of buses, afirst oscillator device that generates first checking signals used forchecking output path and adapted to provide the generated first checkingsignals to at least a first group of the plurality of buses; a secondoscillator device that generates second checking signals used forchecking output path and is adapted to provide the generated secondchecking signals to only a second group of the plurality of buses, thefirst checking signals and the second checking signals different fromeach other; and a checking signal input device that causes the secondchecking signals to be input to the second group of the plurality ofbuses and causes the first checking signals to be input to the firstgroup of the plurality of buses.
 2. A signal switching apparatusaccording to claim 1, wherein the first group of the plurality of busesincludes two or more buses, wherein the second group of the plurality ofbuses includes two or more buses, wherein the plurality of busesconsists of the first group of the plurality of buses and the secondgroup of the plurality of buses, and wherein the second group of theplurality of buses does not include any of the first group of theplurality of buses.
 3. A signal switching apparatus according to claim1, wherein the first checking signals and the second checking signalsrepresent a sine waveform.
 4. A signal switching apparatus comprising: aplurality of buses; a first oscillator device that generates firstchecking signals used for checking an output path and is capable ofproviding the generated first checking signals to one or more buses fromthe plurality of buses; a second oscillator device that generates secondchecking signals used for checking an output path and is capable ofproviding the generated second checking signals to only a group of busesfrom the plurality of buses, wherein the first checking signals and thesecond checking signals are different from each other; a selectingdevice that selects both the first checking signals and the secondchecking signals or only the first checking signals as checking signalsto be input to all of said plurality of buses, and a checking signalinput device that causes the second checking signals to be input to thegroup of buses and the first checking signals to be input to the otherbuses of the plurality of buses if said selecting device selects boththe first checking signals and the second checking signals, and causesthe first checking signals to be input to all of said plurality of busesif said selecting device selects only the first checking signals.
 5. Asignal switching apparatus according to claim 4, wherein the firstchecking signals and the second checking signals represent a sinewaveform.